Digital processing circuitry, and apparatus including such circuitry, is pervasive in modern society to perform a wide range of functions. Such circuitry permits repetitive functions to be carried out at rates much more quickly than the corresponding functions could be performed manually. Large amounts of data, for instance, can be processed at a rapid rate. Such processing of data sometimes includes reading data from, and writing data to, memory locations of a memory device.
A digital computer system, for example, includes a central processing unit and a computer main memory. Memory locations of the computer main memory provide storage locations from which data can be read or to which data can be written. The computer main memory, for instance, is sometimes formed of one or more asynchronous DRAM (Dynamic Random Access Memory) integrated circuits. SRAM (Static Random Access Memory) devices sometimes also form the computer main memory, or a portion thereof. An SRAM device is advantageous because it permits quicker access to the memory locations thereof by making a high-speed locally-accessed copy of the memory available to the central processing unit of the computer system.
Such memory devices are formed on memory locations which form memory arrays. The memory locations of the memory arrays are identified by memory addresses. When memory locations of a memory array are to be accessed, the addresses of the memory locations are provided to decoder circuitry of the memory device. The decoder circuitry decodes the address signals applied thereto to permit access to the memory locations identified by the address signals.
While conventional DRAMs permit relatively quick access to data stored in the memory locations thereof, such as responsive to a read request generated by a computer processing unit, maximum data transmission rates are sometimes limited by the data transmission capacity of a memory bus interconnecting the DRAM and the central processing unit. Using the DRAM together with the central processing unit upon a common substrate, the data transmission rates of a memory bus interconnecting the DRAM and the central processing unit can be increased. Memory accesses by the central processing units to perform read or write operations thereby can be performed at increased rates.
A computer main memory may also be formed of an EDRAM (Enhanced Dynamic Random Access Memory). An EDRAM device includes both a DRAM portion and an SRAM portion. An EDRAM device combines the low cost of a DRAM and provides the high-speed performance of an SRAM. Data is stored in the memory locations of the DRAM portion of the EDRAM. When data stored at selected memory locations of the DRAM is to be read, a memory row of the DRAM containing the selected memory locations is loaded into the SRAM portion of the EDRAM. Once loaded into the SRAM portion, the data is read therefrom. Successive read operations are effectuated in an analogous manner. That is to say, data stored in successive rows of the DRAM portion are loaded into the SRAM portion and then read therefrom. In such manner, the SRAM portion of the EDRAM portion can be of fairly small memory size while still providing the speed advantages associated with SRAM devices. That is to say, the SRAM portion of the EDRAM device need only be of a size of one memory row at which successive rows of data stored in the DRAM portion are successively loaded and successively read.
Conventional EDRAM devices are formed of discrete memory chips, each memory chip having one or more EDRAM banks. The data transmission rate between such an EDRAM device and a central processing unit disposed upon a separate integrated circuit package is sometimes limited by the data transmission capability of a memory bus interconnecting such discrete devices. A manner by which to permit the data transmission rates of data transmitted between an EDRAM and a central processing unit, or other logical device, would increase the rates at which memory read and write operations between the EDRAM and the central processing unit could be performed.
It is in light of this background information related to memory devices that the significant improvements of the present invention have evolved.